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async-fifo
- Verilog codes for asynchrounous fifo design
FIFO
- 是用verilog HDL写的基于FIFO的串口发送机的设计，很详细的代码，很值得学习，已经验证通过-With verilog HDL based on FIFO serial transmitter design, write code, it is worth learning, has been verified by.
fifo-code
- Verilog代码：同步\异步FIFO。包含格雷码计数器.-Verilog code: syncronous\asyncourous FIFO. containing gray counter.
FIFO-and-CAM
- verilog code for gray counter,synchronous and asynchronous fifo
FIFO
- 用verilog做的FIFO程序，仿真通过-FIFO procedures to do with verilog simulation by
fifo
- 这篇文档主要是描述了fifo的作用，里面有用verilog写的源码，及其综合后的结果-This document mainly describes the role of the FIFO inside useful verilog to write source code, and its consolidated results
fifo
- FPGA Verilog语言编写的fifo模块-The fifo module of FPGA Verilog language
sync-and-asyn_FIFO_verilog
- 同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料-Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references
FIFO
- 将ROM的正弦波数据输入FIFO存储器，然后输出，有modelsim仿真波形-Verilog FIFO ROM mif sine
FIFO-[Compatibility-Mode]
- fifo specification for designing verilog
Verilog FIFO
- FPGA的FIFO源代码，经过调试，下载即可用。适合模块调用或嵌入，也适合初学者学习。
uartfifo
- 一个基于verilog的fifo的例子，由数据产生模块产生数据传到fifo中，然后同过发送模块将数据发到上位机上。-One based on the fifo verilog example, by the data generation module generates data to the fifo, and then sent over the same module sends data to the host computer.
FIFO
- 基于FPGA的8位fifo 1s发送10个8位数据，采用的是verilog 编程语言，入门，方便各位学习-Eight fifo based on FPGA 1 s sent 10 8 bits of data, USES is verilog programming language, introduction, convenient for you to learn
FIFO
- sample verilog FIFO design
FIFO
- This a simple example of FIFO(first in and first out) module written in verilog code-This is a simple example of FIFO (first in and first out) module written in verilog code
uart_fifo
- 带fifo的串口通信verilog设计，该设计为学习uart所用，完成PC端发送至fpga后fpga原数据返回，支持长字符串。-Serial communication with fifo verilog design, which is used to learn uart complete PC sends data back to the original post fpga fpga, support long strings.
t4_fifo
- FIFO的verilog与VHDL的实现，并与FIFO的IP核做对比，为了方便大家学习，每个文件均附有测试脚本文件，希望对大家有用。-The FIFO verilog and VHDL implementation with FIFO IP core to do comparison, in order to facilitate learning, each file with a test scr ipt file, we want to be useful.
fifo
- 异步FIFO实现 verilog代码，利用格雷码消除亚稳态-Asynchronous FIFO realize verilog code, Gray code to eliminate the use of metastable
FIFO
- FIFO，先进先出缓冲器，verilog源代码，包括测试代码。-FIFO, FIFO buffer, verilog source code, including test code.
FIFO--verilog
- 同步jk触发器 实现10进制 简单易懂-jk